dnl  Intel P6 mpn_divexact_by3 -- mpn division by 3, expecting no remainder.

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dnl
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include(`../config.m4')


C P6: 8.5 cycles/limb


C The P5 code runs well on P6, in fact better than anything else found so
C far.  An imul is 4 cycles, meaning the two cmp/sbbl pairs on the dependent
C path are taking 4.5 cycles.
C
C The destination cache line prefetching is unnecessary on P6, but removing
C it is a 2 cycle slowdown (approx), so it must be inducing something good
C in the out of order execution.

include_mpn(`x86/pentium/divexact_by3c.asm')
